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A selection of our customers:
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Latest news:
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10-NOV-2009 to 13-NOV-2009:
Productronica - Hall A1 stand 232 (Munich, Germany)
 19-OCT-2009:
PARIS Porte de Versailles Pavillon 7.1
13-OCT-2009:
GOEPEL Technology Day - Register to learn how "TestWay" can reduce your board test and manufacturing costs (Southampton, United Kingdom)
06-OCT-2009 to 08-OCT-2009:
Forum de l'Electronique - Hall 1 stand C 57. Free subscription (Paris-Nord Villepinte, France)
23-JUN-2009:
Newsletter: Get a FREE test coverage analysis!
29-MAR-2009 to 02-APR-2009:
Agilent Technologies to Collaborate with ASTER for Seamless Test Coverage Analysis across Test Platforms. Press release. Visit us at IPC APEX Expo, booth #1245. (California, USA)
03 & 05-MAR-2009:
Goepel Technology Days - Visit ASTER during the seminars in the UK. At Cambridge on the 3rd of March, and at Bristol on the 5th of March, 2009.
05-DEC-2008:
Newsletter: ASTER launches "low-cost" coverage analysis
20-NOV-2008:
ASTER renews the partnership with Mentor Graphics OpenDoor.
11-NOV-2008 to 14-NOV-2008:
Electronica - Hall A1 - Stand 549. (Munich, Germany)
24-OCT-2008:
ASTER Technologies introduces a new generation of "easy to use" test coverage analysis tools. Press release
30-SEP-2008 to 02-OCT-2008:
Forum de l'Electronique - Hall 2 Stand 2-N100. (Paris-Nord Villepinte, France)
09-SEP-2008 to 11-SEP-2008:
Autotestcon - Visit ASTER at the Global Test Solutions booth, stand 930. Information & registration (Salt Lake City, USA)
10-JUL-2008:
Success Stories : KONTRON Testimonial. (Boisbriand, Canada)
17-JUN-2008 to 19-JUN-2008:
National Electronics Week - Visit ASTER at the Accelonix booth, Hall 2, Stand D60. (London, United Kingdom)
10-JUN-2008:
First ASTER Chinese Users' Group - Visit us and share users experience and stay informed about the upcoming products development. English version - Chinese version (Shanghai, China)
26-MAY-2008:
May release of the ASTER Newsletter.
19-MAY-2008:
Accelonix appointed as the official distributor for QUAD, within the UK and Central Europe.
08-APR-2008 to 10-APR-2008:
"Is a board 'good' because the test passes?", technical paper on Board Test Coverage Analysis presented at the Aerospace Testing Seminar 2008. (California, USA)
28-FEB-2008:
Publication of the article Quad - Une solution dédiée rationalise le contrôle de la qualité des cartes in the french magazine 'Electronique International'. (France)
19-FEB-2008:
ASTER appoints Testforce as Distributor in Canada. (Toronto, Canada)
13-NOV-2007 to 16-NOV-2007:
Productronica - Hall A1 - Stand 452 (Munich, Germany)
25-SEP-2007 to 27-SEP-2007:
Electronics Forum - Hall 7.2 - Stand R98 (Paris, France)
22-JUN-2007:
ASTER Technologies benefit from Microsoft Empower to develop QuadView.
15-MAY-2007 to 17-MAY-2007:
Nepcon UK - Stand G46 (Birmingham NEC, United Kingdom)
15-MAY-2007:
ASTER and GOEPEL announce a collaboration for CASCON ScanVision III development.
02-MAY-2007:
May release of the ASTER Newsletter.
28-FEB-2007:
Boundary Scan Day - organised by GOEPEL Electronic (Cambridge University, United Kingdom)
28-FEB-2007:
ASTER and GOEPEL announce DfT Rules Checking collaboration
08-FEB-2007:
Test In Production Event - organised by ACCELONIX, NL (Eindhoven, The Netherlands)
23-JAN-2007:
Read article on "Are your board designs testable?" published on the EngineerLive website.
16-OCT-2006:
ASTER Technologies and TEMENTO Systems announce a strategic partnership
14-SEP-2006:
Functional Board Test - Defect Coverage Analysis, at the 5th IEEE Board Test Workshop. (Fort Collins, Colorado, USA)
19-JUN-2006:
ASTER appoints RDT as Distributor in Israel. (Tel Aviv, Israel)
03-APR-2006:
ASTER opens Direct sales and support Office in the UK. ASTER Technologies Ltd is managed by Peter COLLINS who becomes the sales and marketing manager.
>> More...
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TestWay: Electrical DfT & Fault Coverage Analyzer
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TestWay’s electrical DfT
analyzer enables designers to validate designs at the schematic capture stage,
to ensure that adequate measures have been included to comply with the
manufacturers test requirements. The ability to verify that PCB designs have
been developed with adequate Design-for-Test in mind, is key in
determining the most effective test strategies and accurately calculating fault
coverage, which is crucial in improving competitive advantage, lowering cost and
ensuring product quality.
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How it works
The TestWay open architecture is based on a testability framework that interfaces
to a variety of plug-in modules that provides both import and export opportunities,
as shown below:
Select a block for detailed description.
TestWay reads the board level netlist (schematic or layout) and model
libraries. It then performs a basic topological analysis and symbolic
simulation, and checks each rule, using both topological and accessibility
data.
TestWay will then produce a testability report, written in a natural language
that can be used by design and test engineers to validate that specific DfT criteria
have been implemented.
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Key product benefits
Design rules checking
Verify that specific design rules have been adhered to prior to committing to
PCB layout. Prevent costly design errors at the earliest possible opportunity.
DfT rules checking
Verify that DfT requirements are adhered to in order to maximize test coverage
aligned to the PCB manufacturers test flow. Provide In-Circuit test rules to
insure partitioning and initialization pin controllability; Boundary-Scan test rules
to check Boundary Scan path integrity (JTAG), test bus control and correct
termination etc.Custom rules checking
Define and implement your own Customer’s rules rules
that reflect your company or customer's specific testability requirements.
Test point saving
Identify nets not requiring physical test access and only place test points where
absolutely necessary. TestWay balances the different test approaches provided by
AOI, AXI, BST, FT, FPT, ICT etc, and optimizes
the number of mandatory test accesses, resulting in fewer test probes and
significantly reduces test
fixturing costs due to less complex fixtures.Test coverage estimation
Maximize test and inspection coverage by estimating coverage aligned to test
strategy. Perform ‘what-if’ analysis to select optimal test strategy to achieve
maximum coverage based on historical DPMO data and eliminate redundant test steps.
The resultant test coverage analysis can be viewed either graphically
within the viewer, or as a test coverage report
(PDF file, 54k)
Test coverage measurement
Determine real test efficiency against theoretical coverage and identify areas
for improvement.
By reading real test programs or coverage reports, TestWay controls real test
efficiency against estimated coverage, identifying uncovered areas and any
redundant tests.Functional test coverage
Manage functional test as part of the overall test strategy, produce accurate
coverage reports that assists the diagnosis of faulty boards in production and
repair centers.
Test Interface
TestWay generates input files for the following
Boundary-Scan, In-Circuit & Flying-Probe testers including board description
and device models.
Board visualization
Visualize test coverage and customer specific attributes in schematic, layout
and netlist navigation views. This New-Generation Viewer
also provides unique digitization feature that creates schematic view from PDF.
Advanced reporting
Produce comprehensive reports in a variety of formats that highlight predicted
production yield, test coverage by component type, predict placement time, etc.
Cost modeling
Predict test execution times, total engineering time and calculate hardware
costs such as; test fixture, power supply, spring probes, wiring and vector-less
sensors etc.
Tell me more
Additional information
Other products
- QuadView, Next generation viewers
- TPQR, Test Program Quality Report
- Quad, Quality advisor and manager
- QuadFeederSafe, make your feeder settings secure
- WildScan, Boundary-Scan test translation
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